Replace QLF_NIL with QLF_UNUSED for qualifier sequence list padding.
This splits apart distinct qualifier meanings, and simplifies detection
of empty qualifier sequences.
Some uses of AARCH64_OPND_QLF_NIL actually represent an unknown operand
qualifier. The F_STRICT flag was added to disable the wild card
behaviour for most SVE instructions, but this just makes the code less
consistent and more confusing.
Add a new qualifer to indicate that the real qualifier is currently
unknown, and use this in any place where we need the wildcard behaviour
(and in a few other places where UNKNOWN is more descriptive than NIL).
For consistency (and as an extra check during development), change the
default qualifier value during parsing to AARCH64_OPND_QLF_ERR, and add
explicit qualifier assignments to each non-failure code path.
Add fallback handling for an invalid choice of opd0_qlf, instead of
hitting an assert when trying to use X registers in byte or half
instructions.
Additionally, simplify the code by inlining the relevant parts of
aarch64_get_expected_qualifer, and by deducing the array index directly
from the qualifier enum values (instead of looking up the element size
and computing its log).
This makes aarch64_get_expected_qualifier unused, so remove it.
Add a new opcode flag F_REQUIRES_SP and use that to enforce the
requirement for at least one SP operand in the mov (to/from SP) opcode.
This requirement was the only reason for the existence of the QLF_SP and
QLF_WSP qualifiers. Delete them, and remove the confusing code that
would switch between SP and non-SP qualifiers in the middle of qualifier
matching.
The CRn and CRm operands of sysp were unnecessarily constrained to the
ranges C8-C9 and C0-C7. This constraint has been removed from the
architecture spec, and was never implemented in LLVM, so remove it here
as well.
Additionally, add some more tests to cover the full range of valid sysp
operands, including omitting the pair of optional operands.
These accept either r or w prefix registers during assembly
(pseudoc dialect), while disassembling canonically as r registers.
This eliminates the need for duplicate opcode table entries for
instructions that accept both w and r register forms.
Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>
The BPF "may_goto" instruction is a special sort of conditional jump
where the condition is determined by the BPF runtime. That is, it is
a no-op until the runtime decides otherwise.
For normal asm syntax, the mnemonic "jcond" is chosen in keeping with
the style of following the opcode definitions in the Linux kernel uapi
BPF headers.
This instruction is not currently emitted by GCC, but it can be inserted
into BPF programs via macros defined in the Linux kernel.
PR gas/32176
include/
* opcode/bpf.h (BPF_CODE_JCOND): New.
(bpf_insn_id): Add BPF_INSN_JCOND.
opcodes/
* bpf-opc.c: Add entry for BPF_INSN_JCOND.
gas/testsuite/
* gas/bpf/bpf.exp: Run new dump tests.
* gas/bpf/jcond-be-pseudoc.d: New.
* gas/bpf/jcond-be.d: New.
* gas/bpf/jcond-pseudoc.d: New.
* gas/bpf/jcond-pseudoc.s: New.
* gas/bpf/jcond.d: New.
* gas/bpf/jcond.s: New.
TLBI Domains feature changes TLBI and TLBIP system instructions.
For all TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS*
instructions that are currently dependent on FEAT_D128 (+d128),
will also be available with FEAT_TLBID (+tlbid).
TLBI Domains feature changes TLBI and TLBIP system instructions.
For the TLBI instruction with optional register argument
<Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to
have an Rt value which is not 0b11111 and this is allowed for
all the TLBI instructions with a <type> of ALLE1*, ALLE2*,
VMALL*, VMALLS12* or VMALLWS2* and a <shareability> of IS or OS.
This patch add support for FEAT_TLBID feature, which is enabled
by new +tlbid option.
This patch adds support for MLB invalidate (MLBI) instruction.
Syntax: MLBI <mlbi_op>{, <Xt>}
This instruction is an alias to "SYS #4, C7, C0, #<op2>{, <Xt>}"
and MLBI being the preferred disassembly.
The following list of MLBI operations are supported in this patch for the
MLBI instructions enabled by "+mpamv2"
* alle1
* vmalle1
* vpide1
* vpmge1
This patch adds support for PLB invalidate operation (PLBI) instruction
and the corresponding system registers as operand (<plbi_op>).
Syntax: PLBI <plbi_op>{, <Xt>}
This instruction is an alias to "SYS #<op1>, C10, <Cm>, #<op2>{, <Xt>}"
and PLBI being the preferred disassembly.
The following list of system registers are supported in this patch for the
PLBI instructions enabled by "+poe2" flag and also the "nxs" variants of
these system registers are enabled by "+poe2+xs" flag.
* alle1
* alle1is
* alle1os
* alle2
* alle2is
* alle2os
* alle3
* alle3is
* alle3os
* aside1
* aside1is
* aside1os
* permae1
* permae1is
* permae1os
* perme1
* perme1is
* perme1os
* perme2
* perme2is
* perme2os
* perme3
* perme3is
* perme3os
* vmalle1
* vmalle1is
* vmalle1os
This patch adds support for FEAT_TEV feature enabled by "+tev"
flag along with support for following instructions.
* TENTER
* TEXIT
TENTER instruction uses the existing AARCH64_OPND_NOT_BALANCED_17 operand
to handle the not_balanced (NB) argument , where as a new operand
AARCH64_OPND_NOT_BALANCED_10 is added to support the NB (not_balanced)
argument in TEXIT instruction.
This patch adds support for FEAT_S1POE2 feature enabled by "+poe2"
flag along with support for following instructions.
* TCHANGEB (immediate)
* TCHANGEB (register)
* TCHANGEF (immediate)
* TCHANGEF (register)
A new operand AARCH64_OPND_NOT_BALANCED_17 is added to the code in this
patch to support the new optional argument "NB" (not_balanced) which
is a 1-bit field in the encoding for all the above mentioned
instructions.
Co-authored-by: Matthew Malcomson <matthew.malcomson@arm.com>
Avoid warnings about invalid escapes in etc/update-copyright.py by
using raw strings, add BinutilsFilter to skip psql.rc and add
"Kalray SA." as another copyright holder.
This patch includes:
- The feature flag for the FEAT_F16F32MM feature.
- Instruction FMMLA Half-precision matrix multiply-accumulate to single-precision.
This includes the instructions for the F16F32DOT feature:
- FDOT half-precision to single-precision, by element
- FDOT half-precision to single-precision, vector
ud ui5, also known as amswap.w rd,$r1,rj(rd==rj), is displayed as
"ud ui5" by default during disassembly. Alternatively, the original
instruction can be printed using the objdump -M no-aliases.
To implement this support, a format specifier "ru0:5,ru5:5" for ud is
applied exclusively during disassembly. This specifier indicates that
registers should be printed using their corresponding numeric values,
and when the instruction is identified as ud, only a single parameter
is displayed.
binutils/
* testsuite/binutils-all/loongarch64/dis-amswap-ud-noaliases.d:
New test.
* testsuite/binutils-all/loongarch64/dis-amswap-ud.d: New test.
* testsuite/binutils-all/loongarch64/dis-amswap-ud.s: New test.
gas/
* testsuite/gas/loongarch/macro_ud.d: Update test.
include/
* opcode/loongarch.h: New macro.
opcodes/
* loongarch-dis.c (get_loongarch_opcode_by_binfmt): Correct match `ud`.
(dis_one_arg): Disassemble the `ud` parameter.
* loongarch-opc.c: Add opcode for "ud" alias.
This patch adds support for new BTI <target> "r" (instruction: bti r),
which is an alias to "bti" (with no target), for both "bti" and "bti r"
the preferred disassembly is "bti r". This "bti r" instruction is by
default available from Armv8-A architecture.
The HINT_OPD_F_NOPRINT macro has become redundant with these changes
and has been removed.
In the "ud ui5" macro, the value of ui5 must be in the range 0–31. It
expands to "amswap.w $rd, $r1, $rj", where ui5 specifies the register
number for $rd in the amswap.w instruction, and $rd == $rj.
The test case have been adjusted to no longer report errors for illegal
operands of the amswap.w instruction.
gas/
* config/tc-loongarch.c (check_this_insn_before_appending): No
longer check amswap.w.
* testsuite/gas/loongarch/illegal-operand.l: Update.
* testsuite/gas/loongarch/illegal-operand.s: Update.
* testsuite/gas/loongarch/macro_ud.d: New test.
* testsuite/gas/loongarch/macro_ud.s: New test.
include/
* opcode/loongarch.h: Add new macro for amswap.w.
opcodes/
* loongarch-opc.c: Add macro for ud.
This field is used differently during assembly and disassembly. It
would be nice if we could make this more consistent, but for now just
extend the comment to explain what is going on.
Currently some of the instructions in bitmanip extensions can not be obtained
using DECLARE_INSN macros. I generated them using riscv-opcodes and added to
other opcodes.
Approved-By: Nelson Chu <nelson@rivosinc.com>
A check in print_insn_aarch64_word asserted that part of the encoding
space couldn't contain any valid encodings, and then returned ERR_NYI
("Not Yet Implemented", perhaps?) for these values. However, some of
the new FEAT_MOP4 instructions will trigger the assert. The check seems
to be outdated, and is clearly no longer valid, so it can just be
deleted.
Additionally, there are no other assignments of ERR_NYI, so delete all
remaining references to this error type.
Add new instructions from the Generic Interrupt Controller, GICv5,
extension. These instructions are aliases to system instructions and are
the following:
* gic <operation>, <reg>
* gicr <reg>, <operation>
* gsb <operation>
Generic Interrupt Controller v5, GICv5, adds new system registers
and system instructions. These are enabled with the +gcie flag, where
gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt
Extension.
Many feature bits were unnecessarily added for features with no command
line flags, and effectively acted as aliases of the architecture version
bit they were linked to. The system register regating patch removed all
uses of these feature bits, so we can just remove them.
The flag is unnecessary, because we can just unconditionally check the
features field every time. Having the information duplicated in two
separate fields makes it harder to maintain, particularly in the context
of the upcoming regating patch.
The reg_flags parameter of aarch64_sys_ins_reg_supported_p is now
unused, so remove that as well.
