The Xtensa disassembler enabled the ESP32-S3 SIMD/AI (ee.*) and HiFi3 ops for
every target because the subtarget feature gates were stubbed to return true
(Xtensa_getFeatureBits and hasDensity/hasESP32S3Ops/hasHIFI3). As a result, on a
non-ESP32-S3 Xtensa config any instruction with op0=0xE/0xF was matched as a
4-byte ee.* op, so a base-ISA byte stream desynced.
Make Xtensa_getFeatureBits map the mode to a feature set (mirroring the SystemZ
precedent), thread MI->csh->mode into the three has*Ops gates, and add an opt-in
CS_MODE_XTENSA_ESP32S3. Base/esp32/esp32s2/esp8266 no longer emit ESP32-S3 ops;
CS_MODE_XTENSA_ESP32S3 preserves them. Concrete instance of issue #1992.
The saved auto-sync patch hashes are updated so the fix survives the next LLVM
re-sync. Adds tests/MC/Xtensa/esp32s3.s.yaml.
Co-authored-by: Denys Melnyk <denys@com2cloud.com>
Add CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM to print shifted
MOVN and MOVZ instructions in their explicit forms instead of using
the equivalent MOV aliases.
Keep the existing LLVM-compatible alias output as the default, and
retain MOV aliases for unshifted instructions when the option is
enabled.
Expose the option through cstool and the Python bindings, and add
regression tests for MOVN, MOVZ, 32-bit and 64-bit forms.
Fixes#2890
Signed-off-by: Amaan Mujawar <amaansmujawar@gmail.com>
All the enum names were prefixed with `Alpha` instead of `ALPHA`.
That happened because of an old Auto-Sync bug.
Sadly, I just recognized that Alpha was generated with it.
No idea why it got through in the PR in the first place.
I really would like that to have fixed before Beta.
And while it is super annoying for everyone to fix,
it is better to do as early as possible.
A simple command to replace all these occurrences in your code base is:
```
find . -type f -regex ".*\.\(c\|h\)$" -exec sed -i -E "s|Alpha_([A-Z0-9_]+)|ALPHA_\1|g" {} +
```
Please excuse the inconvenience!
* Implements load libcapstone.so with RTLD_DEEPBIND in the Python bindings. #2912
* remove RTLD_DEEPBIND magic number
* remove extra if/else
* use getattr in case os.RTLD_DEEPBIND is not defined
* Add support for M68060 architecture in M68K disassembler and tests
Add disassembly support for CAS instruction in M68060 and update tests
Add support for M68K CPU32 mode and new instructions
- Introduced CS_MODE_M68K_CPU32 to support the M68K CPU32 architecture in the Python bindings and C headers.
- Updated the instruction table generator to include new CPU32-specific instructions: `bgnd`, `tbls`, `tblu`, `tblsn`, and `tblun`.
- Enhanced the instruction decoding logic in `cs.c` to account for CPU32 mode.
- Added test cases for new instructions and ensured compatibility with existing M68K modes.
- Updated YAML test files to validate the behavior of new instructions under different M68K modes.
fix(M68K): fix cross-arch bugs in cpush/cinv and dc.w printing
build_cpush_cinv: use op1->reg instead of op1->imm for address
register operand. Writing to imm (uint64_t) when reg (m68k_reg,
uint32_t) is read back causes garbage values on big-endian targets
(PPC64, s390x) due to union byte order mismatch.
M68K_printInst: cast imm to uint32_t before passing to PRIx32
format. Passing uint64_t to a PRIx32 format specifier is UB; on
32-bit big-endian MIPS the high word (0) is read instead of the
low word containing the instruction bytes.
Fixes cstest details failures on QEMU Linux PPC64, s390x, Mips32.
run clang-format
fix[m68k]: ori build_imm_ea
fix[m68k]: btst
fix[m68k]: cast immediate values to unsigned int in build_imm_ea functions
* fix get_with_index_address_mode
* - Replaced specific assembly instructions with `dc.w` for invalid cases.
- Added new test cases for SBCD, PACK, UNPK, CHK.L, and coprocessor instructions to ensure correct behavior across different CPU models.
- Ensured that invalid instructions for CPU32 and 68000 are correctly identified.
- Updated expected outputs for fsdiv and PMMU related instructions to reflect their validity on specific architectures.
* Fix CMake test command to use target file reference for integration tests
* Refactor PMOVE instruction comments for clarity and accuracy in m68k.yaml
* Add tests for bitfield instructions and PC-relative addressing in m68k.yaml
* Refactor M68K instruction printing and enhance bitfield support
- Improved the M68K instruction printer by refactoring the handling of register bits and addressing modes.
- Introduced new functions for printing scale factors, index registers, and immediate values.
- Enhanced bitfield handling in the `m68k_op_mem` structure to support both static and register-encoded values.
- Updated tests to reflect changes in instruction formatting, particularly for `cinvl`, `cpushl`, and `cas2` instructions.
- Added new test cases for bitfield instructions to ensure correct parsing and output.
- Add details to tests/m68k.yaml
* Fix type casting for immediate values in addressing modes and enhance m68k architecture support in cstool
* Refactor type usage for immediate values and enhance switch handling in M68K disassembler
- Replace int with uint32_t for immediate values, register lists, and related parameters to ensure correct type handling and consistency.
- Add default cases to switch statements for improved robustness.
- Update bitfield printing to use explicit PRId8 formatting for clarity.
- Refactor detail handling in M68KInstPrinter to use helper functions for detail access.
- Minor code cleanups and improved type safety throughout disassembler logic.
* m68k: update v6 guide
* RISC-V: add reg_access and test its usages in C and Python
reg_access is a convenience wrapper over the `operands` array that filters the register operands (including those used as memory base address) and returns them sorted into read
and written registers. It wasn't implemented for RISC-V, this PR implements it.
The following decisions were made for RISC-V:
1- System registers (CSRs) are not registers
This follows existing Capstone convention, where almost every archiceture that have system registers except x86 treats them as a seperate address space.
From a purely practical POV, the reg_access function API returns registers as an array of integers, and the address space of normal registers intersects with that of system registers
so there is nothing in the return value to distinguish them.
2- PC is not an implicit register
Whenever an instruction reads PC (e.g. all call-ish instructions JAL[R]?) this is NOT counted as an implicit read of the PC.
The reason is that the PC is somewhat "second class" in RISC-V, it's an archiectural register but has no actual index and can never be directly written to by any instruction in any
standard extension no matter the privliege.
Meanwhile, all instruction that read the PC have names that make it obvious they read the PC so adding that information to the implicit reads array would be redundant.
* introduce a +noaliascompressed option to selectively enable none-aliasing for compressed instrcution only but leave aliasing for the rest of instructions
* add tests and documentation comments
* fix python bindings and formatting
* add docs
* Extend M680X support to RS08
* Format bindings/python/capstone/__init__.py
---------
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
- Updated to LLVM-18
- Operands have now read/write access information
- Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...)
- Changed register names
* FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F`
and `RISCV_REG_F<n>_D` for n in `0..31`
- Added register names
* Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples
* `RISCV_REG_V21`
* `RISCV_REG_V9_V10`
* `RISCV_REG_V3_V4_V5`
* etc... up to 8-register combinations
* Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31`
- Changed instruction names
* Instructions ending in `_AQ_RL` now end in `_AQRL`
- Added instruction names: massive amount, see `include/capstone/riscv.h`
- Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type`
* `dimm` is used for instructions with FP immediates
* `csr` is used for instructions with CSR systrem registes
- Added ISA flags to turn ISA extensions on and off
* Fix faulty _check().
* Add negative test case for cstest_py
* Enable full leak report and fix leaks.
* Add negative tests to cmake and CI.
* Fix typos
* Update cstest.py logging
* Update cstest.c logging
* Change exception to log+return in TestExpected.compare
The prior change in TestCase.test converts the exception to
TestResult.FAILED which doesn't preserve the status here.
* Restore calling sequence in TestCase.test
The transformation didn't preserve error reporting. It also is
unnecessary now that TestExpected.compare returns a TestResult again.
* Convert exception to return for length check in TestExpected.compare
The callsite in TestCase.test no longer converts exceptions to a
TestResult.
* Rename local variable 'postfix' to 'prefix' in test_input_stringify
This better reflects what it actually is.
* Enable cstest/cstest_py to test for instruction size.
* Add missing operand->size check for x86 details.
* Use tbool instead of int for unity across code.
* Fix: operand->size is optional.
- Bump cibuildwheel to 3.1.3
- Support free-threaded CPython build for python 3.14
- Remove 3.6 and 3.7 from cibw_skip since they are skipped by default by the newer cibuildwheel
* Fix invalid bounds check and return NULL in case of OOB.
* Prevent duplication of memory operands.
* Increase maximum op count for Sparc
* Fix Mips instructions with more than 10 operands.
* Add Sparc inc fils, delete old files and update AS with Sparc config.
* AS: Refuse to run differ if an old file is missing.
* AS: Refer to the RefactorGuide.md
* Add first translated Sparc files.
* Fixup SparcMCTargetDesc.h
* Fixup SparcDisassembler.h
* Fixup instruction printer.
* Fixup SparcInstPrinter
* Basic functions of Capstone module
* Fix SP sparc namespace prefix.
* Fix build script and linking
* Fix disassembler not actually reading bytes.
* Match \!encoding in llvm-mc output (Sparc has this).
* Add Sparc LE and and make v9 a feature to enable.
* Update test files for Sparc
* Fix tests.
* Add assembly tests
* AS: Add settings to use assembly tests.
* Test fixes
* Fix typos
* Add reg and imm details.
* Add mem details and instruction formats.
* Handle condition codes.
* Formatting
* Add hints.
* Add membar and asi tags
* Update Python bindings
* Add asi and membar to cstest
* Restructure test file
* Capstone fix for llvm-project/#139284.
* Fix branch detail tests
* Handle faulty mem operand defintions.
* Add membar and asi tests
* Add one more branch instruction test.
* Add missing call alias
* Fix tests.
Updated after fixing branch disponents.
Issues with the generated assembly tests. The assembly tests don't check the feature flags enabled. And hence V9 tests are added to the none V9 test file.
* Fix alias lookup with , in the asm_text
* Fix common detail tests.
* Fix issue.yaml
* Add Sparc changelog
* Add changelog for Sparc to v6 guide
* Fix incorrect translated array size check.
* Reading the ISA and thinking would help...
This is not how alignment is calculated -.-
* Fix call targets
* Remove 'real' BA instruction (which is only an alias).
* Add missing property getters.
* Add missing format details
* Set correct detail struct
* Support access detail testing for Sparc.
* Add hard-coded special registers tbr, wim, psr
* Add alias tests for call and ba.
* Fix copy paste mistake.
* Add note about big/little endian into guide.
* Add implied flag for SparcV9
* Format
* Store CC field consistently in an extra field.
The CC field used was sometimes stored as register,
sometimes as not at all.
Now it is consistently stored in a separated field.
* Add an invalid ASI tag.
* Fix LDSTUB/A memory access and incorrect operand details.
* Handle condition codes more elegantly.
Also fixes bugs with wrong cc fields, or missing fields.
* Add separation ; character for assembly tests.
* Apply fix from llvm-project/#143232
* Use enum types for memory operands
* Update Pythyon constants
* Xtensa: use cs_xtensa_op_type for operand type, and use cs_ac_type for operand access mode
To explicitly tell the user the possible values of the operand
type/access mode.
Also drop the unused XTENSA_OP_MEM_REG and XTENSA_OP_MEM_IMM.
* Use cs_ac_type for operand access mode in all arches
Currently, some arches use uint8_t for operand access mode, while others
use cs_ac_type. Use cs_ac_type uniformly.
* M680X: use cs_ac_type directly, instead of adding another e_access type
* Change access type to c_uint to follow c-side changes to cs_ac_type
* Document operand access type change to enum
The following constants are undefined in `capstone/include/capstone/riscv.h`.
So, remove them as those were commented in `riscv.h`.
Signed-off-by: Leon Hwang <leon.hwang@linux.dev>
* Enhance shift value and types of shift instructions.
Shifts via registers now save the register id in cs_arch64_op.shift.value
and set the shift type accordingly.
* Sort table
* Add arm64.py and sysz_const.py compatibility layer to the Python bindings
When importing `capstone.arm64` before doing other capstone imports the ARM64 constants get monkey patched into the exports.
Same with `capstone.sysz_const` for the SYSZ constants.
* Add SPDX-License comments
* Access an instruction detail in compatibility test
* Fail python tests on error instead of just ERROR output
Include the test_iter.py in the test_all.py too.
* Improve python compatibility docs
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Test for ARM_CC_* constants presence
---------
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
