The Xtensa disassembler enabled the ESP32-S3 SIMD/AI (ee.*) and HiFi3 ops for
every target because the subtarget feature gates were stubbed to return true
(Xtensa_getFeatureBits and hasDensity/hasESP32S3Ops/hasHIFI3). As a result, on a
non-ESP32-S3 Xtensa config any instruction with op0=0xE/0xF was matched as a
4-byte ee.* op, so a base-ISA byte stream desynced.
Make Xtensa_getFeatureBits map the mode to a feature set (mirroring the SystemZ
precedent), thread MI->csh->mode into the three has*Ops gates, and add an opt-in
CS_MODE_XTENSA_ESP32S3. Base/esp32/esp32s2/esp8266 no longer emit ESP32-S3 ops;
CS_MODE_XTENSA_ESP32S3 preserves them. Concrete instance of issue #1992.
The saved auto-sync patch hashes are updated so the fix survives the next LLVM
re-sync. Adds tests/MC/Xtensa/esp32s3.s.yaml.
Co-authored-by: Denys Melnyk <denys@com2cloud.com>
Add CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM to print shifted
MOVN and MOVZ instructions in their explicit forms instead of using
the equivalent MOV aliases.
Keep the existing LLVM-compatible alias output as the default, and
retain MOV aliases for unshifted instructions when the option is
enabled.
Expose the option through cstool and the Python bindings, and add
regression tests for MOVN, MOVZ, 32-bit and 64-bit forms.
Fixes#2890
Signed-off-by: Amaan Mujawar <amaansmujawar@gmail.com>
* Add ColdFire EMAC_B dual-acc MAC support
* Fix M68K reserved EA decoding in Capstone
---------
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
All the enum names were prefixed with `Alpha` instead of `ALPHA`.
That happened because of an old Auto-Sync bug.
Sadly, I just recognized that Alpha was generated with it.
No idea why it got through in the PR in the first place.
I really would like that to have fixed before Beta.
And while it is super annoying for everyone to fix,
it is better to do as early as possible.
A simple command to replace all these occurrences in your code base is:
```
find . -type f -regex ".*\.\(c\|h\)$" -exec sed -i -E "s|Alpha_([A-Z0-9_]+)|ALPHA_\1|g" {} +
```
Please excuse the inconvenience!
* Alpha: fix integer register class decoding order
GPRC[] is LLVM's register allocation order, not the architectural
register number order. Using it to map hardware register fields 0-31
scrambled r9-r29 (e.g. field 9 → \$16, field 23 → \$9).
Alpha_R0 through Alpha_R31 are contiguous in the enum (33-64), so
Alpha_R0 + RegNo gives the correct architectural mapping directly.
Update existing tests that encoded the wrong register names, and add
new MC tests covering the previously scrambled r9-r29 range.
* Alpha: fix BR/BSR to accept any Ra register
The LLVM decoder table constrained BR to Ra=31 and BSR to Ra=26,
rejecting all other encodings as illegal. The Alpha ISA defines Ra
as the return address destination for BSR (any writable register
is valid) and as an unused hint field for BR (any register field
is legal in existing binaries).
Remove both CheckField constraints by zeroing the skip bytes to a
no-op, and change the decode format from 25 (disp-only) to 27
(Ra + disp21) so the Ra operand is visible to callers.
Override BR/BSR in the instruction printer, since the generated
AsmWriter hardcodes "\$31" for BR and ignores Ra entirely for BSR.
Update the placeholder BSR test (which had a malformed expected
string) and add new tests for BR/BSR with non-default Ra values.
Refs: https://github.com/capstone-engine/capstone/issues/2582
* Alpha: fix CALL_PAL to decode full 26-bit function code
The LLVM decoder mapped opcode 0x00 to COND_BRANCH_I (format 0),
which tried to interpret bits[20:0] as a register number. This
failed for any PAL function code > 31 (e.g. 0x83 gentrap, 0x1020b).
Add decode format 31 that extracts bits[25:0] as a single immediate,
switch opcode 0x00 to use it, map COND_BRANCH_I to the new public
Alpha_INS_CALL_PAL, and override the printer to emit "call_pal <imm>".
* Alpha: fix JMP/JSR to accept any Ra, Rb, and hint
The LLVM decoder required JMP to have Ra=31 and hint=0, and JSR to
have specific Ra/Rb pairs (26/27 or 23/27) with hint=0. Real-world
code uses arbitrary combinations: JMP with Ra!=31 to save return
addresses, JSR with Ra=26 and Rb!=27, or non-zero hint fields for
branch prediction.
Remove all Ra, Rb, and hint constraints for JMP and JSR. Switch both
from decode format 17 (Rb only) and 14 (no operands) to format 18
(Ra + Rb + hint14). Add printer override to emit the three-operand
form: "jmp/jsr \$ra,(\$rb),hint".
Closes: https://github.com/capstone-engine/capstone/issues/2582
* Alpha: fix TRAPB/EXCB/MB/WMB to decode with any Ra/Rb field
The LLVM assembler emits these barrier instructions with Ra=Rb=31,
but the decoder required Ra=Rb=0 (bits[25:16]=0), causing all
canonical encodings to fail.
Remove the CheckField constraint so any Ra/Rb combination is accepted.
The instructions carry no register operands in their decode format,
so the field values do not affect the output.
Closes: https://github.com/capstone-engine/capstone/issues/2795
* Alpha: add missing test coverage for s4addq and cvt FP variants
s4addq (register and literal forms), cvttq/svc, cvtts/sui, cvtqs/sui,
and cvtqt/sui had no MC tests despite being reachable instructions.
* Alpha: fix RET/RC/RS to decode with any register fields
RET (opcode 0x1a, bits[15:14]=10) shares identical operation semantics
with JMP/JSR/JSR_COROUTINE — all four differ only in branch-prediction
hints. The decoder incorrectly required Ra=31, Rb=26, hint=1 exactly;
any other encoding failed to decode.
RC and RS (opcode 0x18) have an unused Rb field. The decoder checked
Rb==0 (R0), but convention is to set unused fields to R31 (=31), so
any real-world encoding produced by a compiler would fail to decode.
Remove the restrictive CheckField constraints on RET, RC, and RS.
Update RETDAG's operand table to carry Ra+Rb+hint (format 18), and
add a ret printer in Alpha_LLVM_printInstruction matching the existing
jmp/jsr handling.
Tests added: ret $0,($1),3 (non-canonical RET); rc/rs $1 with Rb=R31.
* Add support for M68060 architecture in M68K disassembler and tests
Add disassembly support for CAS instruction in M68060 and update tests
Add support for M68K CPU32 mode and new instructions
- Introduced CS_MODE_M68K_CPU32 to support the M68K CPU32 architecture in the Python bindings and C headers.
- Updated the instruction table generator to include new CPU32-specific instructions: `bgnd`, `tbls`, `tblu`, `tblsn`, and `tblun`.
- Enhanced the instruction decoding logic in `cs.c` to account for CPU32 mode.
- Added test cases for new instructions and ensured compatibility with existing M68K modes.
- Updated YAML test files to validate the behavior of new instructions under different M68K modes.
fix(M68K): fix cross-arch bugs in cpush/cinv and dc.w printing
build_cpush_cinv: use op1->reg instead of op1->imm for address
register operand. Writing to imm (uint64_t) when reg (m68k_reg,
uint32_t) is read back causes garbage values on big-endian targets
(PPC64, s390x) due to union byte order mismatch.
M68K_printInst: cast imm to uint32_t before passing to PRIx32
format. Passing uint64_t to a PRIx32 format specifier is UB; on
32-bit big-endian MIPS the high word (0) is read instead of the
low word containing the instruction bytes.
Fixes cstest details failures on QEMU Linux PPC64, s390x, Mips32.
run clang-format
fix[m68k]: ori build_imm_ea
fix[m68k]: btst
fix[m68k]: cast immediate values to unsigned int in build_imm_ea functions
* fix get_with_index_address_mode
* - Replaced specific assembly instructions with `dc.w` for invalid cases.
- Added new test cases for SBCD, PACK, UNPK, CHK.L, and coprocessor instructions to ensure correct behavior across different CPU models.
- Ensured that invalid instructions for CPU32 and 68000 are correctly identified.
- Updated expected outputs for fsdiv and PMMU related instructions to reflect their validity on specific architectures.
* Fix CMake test command to use target file reference for integration tests
* Refactor PMOVE instruction comments for clarity and accuracy in m68k.yaml
* Add tests for bitfield instructions and PC-relative addressing in m68k.yaml
* Refactor M68K instruction printing and enhance bitfield support
- Improved the M68K instruction printer by refactoring the handling of register bits and addressing modes.
- Introduced new functions for printing scale factors, index registers, and immediate values.
- Enhanced bitfield handling in the `m68k_op_mem` structure to support both static and register-encoded values.
- Updated tests to reflect changes in instruction formatting, particularly for `cinvl`, `cpushl`, and `cas2` instructions.
- Added new test cases for bitfield instructions to ensure correct parsing and output.
- Add details to tests/m68k.yaml
* Fix type casting for immediate values in addressing modes and enhance m68k architecture support in cstool
* Refactor type usage for immediate values and enhance switch handling in M68K disassembler
- Replace int with uint32_t for immediate values, register lists, and related parameters to ensure correct type handling and consistency.
- Add default cases to switch statements for improved robustness.
- Update bitfield printing to use explicit PRId8 formatting for clarity.
- Refactor detail handling in M68KInstPrinter to use helper functions for detail access.
- Minor code cleanups and improved type safety throughout disassembler logic.
* m68k: update v6 guide
* introduce a +noaliascompressed option to selectively enable none-aliasing for compressed instrcution only but leave aliasing for the rest of instructions
* add tests and documentation comments
* fix python bindings and formatting
* add docs
* Extend M680X support to RS08
* Format bindings/python/capstone/__init__.py
---------
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
- Updated to LLVM-18
- Operands have now read/write access information
- Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...)
- Changed register names
* FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F`
and `RISCV_REG_F<n>_D` for n in `0..31`
- Added register names
* Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples
* `RISCV_REG_V21`
* `RISCV_REG_V9_V10`
* `RISCV_REG_V3_V4_V5`
* etc... up to 8-register combinations
* Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31`
- Changed instruction names
* Instructions ending in `_AQ_RL` now end in `_AQRL`
- Added instruction names: massive amount, see `include/capstone/riscv.h`
- Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type`
* `dimm` is used for instructions with FP immediates
* `csr` is used for instructions with CSR systrem registes
- Added ISA flags to turn ISA extensions on and off
* Add workflow to check for C formatting
Rename run-clang-tidy.sh for consistency with clang-format script
Don't align trailing comments.
It leads to unreproducable formatting.
Reformat some comments leading in-compilable up code after clang-format
Format generated compatibility header.
Add clang-format script
Be more verbose with clean-up scripts and fail early.
Pass clang-format via command line
Install clang-format for the HeaderPatcher
* Format code with clang-format-17
* Fix invalid bounds check and return NULL in case of OOB.
* Prevent duplication of memory operands.
* Increase maximum op count for Sparc
* Fix Mips instructions with more than 10 operands.
* Add Sparc inc fils, delete old files and update AS with Sparc config.
* AS: Refuse to run differ if an old file is missing.
* AS: Refer to the RefactorGuide.md
* Add first translated Sparc files.
* Fixup SparcMCTargetDesc.h
* Fixup SparcDisassembler.h
* Fixup instruction printer.
* Fixup SparcInstPrinter
* Basic functions of Capstone module
* Fix SP sparc namespace prefix.
* Fix build script and linking
* Fix disassembler not actually reading bytes.
* Match \!encoding in llvm-mc output (Sparc has this).
* Add Sparc LE and and make v9 a feature to enable.
* Update test files for Sparc
* Fix tests.
* Add assembly tests
* AS: Add settings to use assembly tests.
* Test fixes
* Fix typos
* Add reg and imm details.
* Add mem details and instruction formats.
* Handle condition codes.
* Formatting
* Add hints.
* Add membar and asi tags
* Update Python bindings
* Add asi and membar to cstest
* Restructure test file
* Capstone fix for llvm-project/#139284.
* Fix branch detail tests
* Handle faulty mem operand defintions.
* Add membar and asi tests
* Add one more branch instruction test.
* Add missing call alias
* Fix tests.
Updated after fixing branch disponents.
Issues with the generated assembly tests. The assembly tests don't check the feature flags enabled. And hence V9 tests are added to the none V9 test file.
* Fix alias lookup with , in the asm_text
* Fix common detail tests.
* Fix issue.yaml
* Add Sparc changelog
* Add changelog for Sparc to v6 guide
* Fix incorrect translated array size check.
* Reading the ISA and thinking would help...
This is not how alignment is calculated -.-
* Fix call targets
* Remove 'real' BA instruction (which is only an alias).
* Add missing property getters.
* Add missing format details
* Set correct detail struct
* Support access detail testing for Sparc.
* Add hard-coded special registers tbr, wim, psr
* Add alias tests for call and ba.
* Fix copy paste mistake.
* Add note about big/little endian into guide.
* Add implied flag for SparcV9
* Format
* Store CC field consistently in an extra field.
The CC field used was sometimes stored as register,
sometimes as not at all.
Now it is consistently stored in a separated field.
* Add an invalid ASI tag.
* Fix LDSTUB/A memory access and incorrect operand details.
* Handle condition codes more elegantly.
Also fixes bugs with wrong cc fields, or missing fields.
* Add separation ; character for assembly tests.
* Apply fix from llvm-project/#143232
* Use enum types for memory operands
* Update Pythyon constants
* Xtensa: use cs_xtensa_op_type for operand type, and use cs_ac_type for operand access mode
To explicitly tell the user the possible values of the operand
type/access mode.
Also drop the unused XTENSA_OP_MEM_REG and XTENSA_OP_MEM_IMM.
* Use cs_ac_type for operand access mode in all arches
Currently, some arches use uint8_t for operand access mode, while others
use cs_ac_type. Use cs_ac_type uniformly.
* M680X: use cs_ac_type directly, instead of adding another e_access type
* Change access type to c_uint to follow c-side changes to cs_ac_type
* Document operand access type change to enum
The following constants are undefined in `capstone/include/capstone/riscv.h`.
So, remove them as those were commented in `riscv.h`.
Signed-off-by: Leon Hwang <leon.hwang@linux.dev>
* Enhance shift value and types of shift instructions.
Shifts via registers now save the register id in cs_arch64_op.shift.value
and set the shift type accordingly.
* Sort table
* Fix: Set writeback for AddrMode5 operands with W=1
* Fix memory acccess of vector load instructions.
* Remove unused files.
* Fix operands of RFED instructions
They have now memory operand and
the writeback flag is set accordingly.
* Fix: Remove invalid mnemonic enum adr_
* Add missing NULL check
* Update PPC module to LLVM 18.
**New**
(According to LLVM changelog)
- Added DFP instruction.
- Added the SCV instruction.
**Changes**
- Memory decoder were simplified by decoding disponent and base reg separately.
- `DFORM` -> `DFORM_BASE`
- Use inverted `MCInstDesc` table.
- Replace the many declared printer in PPCInstPrinter with `static inlines`.
- Renamed groups to upper case.
- Switched to `ARCH_add_cs_detail_X()` function names.
- Remove `PPCInstPrinter.h` because it is no longer used.
* Fix: Use correct directory name.
* Fix segfaults and add asserts for these NULL cases.
* Allow to map a single LLVM option to multiple CS options
* Add default endian option to the MCUpdater
* Fix setter for Little endian
* Add SPE option to cstool
* Fix QPX instructions.
Due to 4b43ef3e5c
the names of the operands were matched.
Because FRT dosn't exist in the XForm_1 class,
the generated tables didn't decoded them.
* Fix: AbsAddr should be printed as unsigned.
* Fix S12 immediate printing for PC memory operands
* Fix MCUpdater tests
* Update PPCRegisterInfo_stripRegisterPrefix
* Add support for selection of Power versions
* Run clang-format
* Fix feature check
* Allow to overwrite in multi-mode
* Add some more flags
* Fix order and map name
* Add new test files.
* Fix checks for features.
Only enables PowerX feature checks of a Power architecture is enabled
and the feature is in the list of it.
* Print byte sequence with space between comma.
This helps with copy and search of the byte string in the test files.
* Fix tests broken due to feature toggles
* Shorten generated names.
* Update bindings
