PE/COFF stores symbol section numbers in a 16-bit field. Binutils used
signed 16-bit handling there, which limited normal PE objects to 32767
sections even though MSVC and Clang already accept a larger unsigned
range.
Raise the normal PE section limit to 65279, while keeping the PE/COFF
special section-number values for undefined, absolute and debug symbols
working correctly. Do this by decoding and encoding normal PE symbol
section numbers as unsigned values in the ordinary range, but preserving
the reserved PE constants explicitly.
Also add a gas test that exercises a normal PE object above the old
32767-section limit and checks that objdump reports the high section
number correctly.
bfd/ChangeLog:
* coffcode.h (COFF_DEFAULT_MAX_NSCNS): Define.
(bfd_coff_std_swap_table): Use it for the default maximum section
count.
(ticoff0_swap_table): Likewise.
(ticoff1_swap_table): Likewise.
* peXXigen.c (pe_decode_sym_section_number): New function.
(pe_encode_sym_section_number): New function.
(_bfd_XXi_swap_sym_in): Use pe_decode_sym_section_number.
(_bfd_XXi_swap_sym_out): Use pe_encode_sym_section_number.
include/ChangeLog:
* coff/pe.h (IMAGE_SYM_UNDEFINED): Define.
(IMAGE_SYM_ABSOLUTE): Define.
(IMAGE_SYM_DEBUG): Define.
(IMAGE_SYM_SECTION_MAX): Define.
gas/ChangeLog:
* testsuite/gas/pe/pe.exp: Run large-obj-normal.
* testsuite/gas/pe/large-obj-normal.s: New test.
* testsuite/gas/pe/large-obj-normal.d: New test.
Signed-off-by: Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
Add "+sme-f64" to the list of architecture extensions. This has already
been supported in LLVM for several years.
We don't need to update the feature requirements for any opcodes,
because FEAT_SME_FA64 only enables instructions that were already
available in non-streaming mode, and the feature checks don't know what
mode an instruction will be run under.
Disassembly for the OP_MOV_Z_Zi opcode artificially rejected a zero
index value, to indicate that the preferred disassembly uses a different
alias. This is more naturally indicated by specifying the other alias
as a higher priority.
Update the alias priority, and remove the zero check and the now-unused
OP_MOV_Z_Zi enum value.
This patch fixes some style nits:
- Fix indentations
- Using TABs for indentation
- Breaking long lines
- Remove ; after the closing } of a code block
bfd/
* cpu-avr.c: Adhere to GNU coding style.
* elf32-avr.c: Same.
* elf32-avr.h: Same.
gas/
* config/tc-avr.c: Adhere to GNU coding style.
opcodes/
* avr-dis.c: Adhere to GNU coding style.
include/
* opcode/avr.h: Adhere to GNU coding style.
The remaining mpamv2 details only use system registers; so by our
conventions we do not use a feature option to enable them. Remove the
now redundant +mpamv2 architecture option and adjust the tests
accordingly.
Arm has obsoleted the unimplemented TME feature. Warn if instructions
from this feature are encountered.
Also tweak warn_unpredictable_ldst to use const more often, since the
arguments are the same as for the new warn_deprecated function.
This patch supports the RISC-V Zvbdota family of batched dot-product
extensions [1].
Compared to the non-batched Zvdota family, Zvbdota computes up to eight
dot products at a time. These instructions use an EMUL=8 `vs2` vector
register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
This patch adds assembler/disassembler support for those additional
operand constraints.
The Zvbdota extension family includes the following extensions:
* Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
accumulation.
* Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
accumulation.
* Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
with 32-bit accumulation.
* Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
32-bit accumulation.
* Zvfbdota32f: batched dot product of 32-bit single-precision
floating-point numbers with 32-bit accumulation.
[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): New implies.
(riscv_supported_std_z_ext): New extensions.
(riscv_multi_subset_supports): Ditto.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
zvfqwbdota8f and zvfbdota32f extensions.
* config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
type 'q' and 'r' bits validation.
(riscv_vtype_altfmt_supported): Add Zvbdota extensions.
(my_getVsetvliExpression): Update altfmt error message.
(riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
and 'r' operand for ci immediate.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvbdota.d: New test.
* testsuite/gas/riscv/zvbdota.s: Ditto.
* testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
* testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
* testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
* testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
* testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
New encoding.
(MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
(MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
(MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
(MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
(MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (enum riscv_insn_class): New extension classes.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
for Zvbdota.
* riscv-opc.c (riscv_opcodes): New instructions.
Zvfqwdota8f: dot product of 8-bit floating-point numbers with 32-bit accumulation.
Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8 of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew constants for vsetvli/vsetivli so that assembly code can select the alternative element formats required by these dot-product instructions.
[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): New implies.
(riscv_supported_std_z_ext): New extensions.
(riscv_multi_subset_supports): Ditto.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
zvfqwdota8f extensions.
* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
constants array for e8alt and e16alt.
(riscv_vtype_altfmt_supported): New function.
(my_getVsetvliExpression): Ditto.
* testsuite/gas/riscv/march-help.l: New test.
* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
* testsuite/gas/riscv/zvdota.d: Ditto.
* testsuite/gas/riscv/zvdota.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New encoding.
(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT): New vtype altfmt.
(enum riscv_insn_class): New extension classes.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add altfmt support.
* riscv-opc.c (riscv_opcodes): New instructions.
This patch supports Zalasr extension(load-acquire/store-release) instructions.
https://github.com/riscv/riscv-zalasr
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New ext.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Support Zalasr extension.
* testsuite/gas/riscv/march-help.l: New ext.
* testsuite/gas/riscv/zalasr.d: New test.
* testsuite/gas/riscv/zalasr.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_LBA): New match opcode.
(MASK_LBA): New mask opcode.
(MATCH_LHA): New match opcode.
(MASK_LHA): New mask opcode.
(MATCH_LWA): New match opcode.
(MASK_LWA): New mask opcode.
(MATCH_LDA): New match opcode.
(MASK_LDA): New mask opcode.
(MATCH_SBR): New match opcode.
(MASK_SBR): New mask opcode.
(MATCH_SHR): New match opcode.
(MASK_SHR): New mask opcode.
(MATCH_SWR): New match opcode.
(MASK_SWR): New mask opcode.
(MATCH_SDR): New match opcode.
(MASK_SDR): New mask opcode.
(DECLARE_INSN): New insn declare.
* opcode/riscv.h (enum riscv_insn_class): New ext.
opcodes/ChangeLog:
* riscv-opc.c: New instructions def.
Rename the Arm AEABI CPU architecture tag constants and macro definitions to include the
profile suffix for A-profile architectures. This makes the naming
consistent with existing v8-R and v8-M tag names, while preserving the
existing numeric tag values.
Update BFD, GAS and Gold usage accordingly, including attribute combination
tables, architecture checks, and mach selection.
Replace QLF_NIL with QLF_UNUSED for qualifier sequence list padding.
This splits apart distinct qualifier meanings, and simplifies detection
of empty qualifier sequences.
Some uses of AARCH64_OPND_QLF_NIL actually represent an unknown operand
qualifier. The F_STRICT flag was added to disable the wild card
behaviour for most SVE instructions, but this just makes the code less
consistent and more confusing.
Add a new qualifer to indicate that the real qualifier is currently
unknown, and use this in any place where we need the wildcard behaviour
(and in a few other places where UNKNOWN is more descriptive than NIL).
For consistency (and as an extra check during development), change the
default qualifier value during parsing to AARCH64_OPND_QLF_ERR, and add
explicit qualifier assignments to each non-failure code path.
Add fallback handling for an invalid choice of opd0_qlf, instead of
hitting an assert when trying to use X registers in byte or half
instructions.
Additionally, simplify the code by inlining the relevant parts of
aarch64_get_expected_qualifer, and by deducing the array index directly
from the qualifier enum values (instead of looking up the element size
and computing its log).
This makes aarch64_get_expected_qualifier unused, so remove it.
Add a new opcode flag F_REQUIRES_SP and use that to enforce the
requirement for at least one SP operand in the mov (to/from SP) opcode.
This requirement was the only reason for the existence of the QLF_SP and
QLF_WSP qualifiers. Delete them, and remove the confusing code that
would switch between SP and non-SP qualifiers in the middle of qualifier
matching.
During review, a question was "where are those numbers that you are
adding defined". Add some URLs pointing to the source of truth for
those numbers.
Change-Id: I11b7cb351a9b818fca66a532bfcd27286ec0ddfd
AMDGPU code object V6 adds the EF_AMDGPU_GENERIC_VERSION_V field.
Decode it when decoding the e_flags value for amdgpu.
The output for such generic GFX targets will look like:
$ readelf -h gpu.elf
ELF Header:
...
Flags: 0x1000151, gfx9-generic, xnack any, generic v1
----------
...
... indicating that this ELF has the "generic code object v1" flag.
Change-Id: I0cb8014fc23150e16f43ab98adb3832ede253c88
Co-Authored-By: Simon Marchi <simon.marchi@efficios.com>
This patch updates the list of supported AMDGPU architectures in bfd/
binutils/ and include/elf/.
The following architectures have been added:
- gfx942
- gfx950
- gfx1150
- gfx1151
- gfx1152
- gfx1153
- gfx1200
- gfx1201
- gfx1250
The canonical source for these numbers is:
https://llvm.org/docs/AMDGPUUsage.html#amdgpu-ef-amdgpu-mach-table
Co-Authored-By: Laurent Morichetti <laurent.morichetti@amd.com>
Co-Authored-By: Simon Marchi <simon.marchi@efficios.com>
Co-Authored-By: Olu Ogunbowale <oogunbow@amd.com>
Co-Authored-By: Shahab Vahedi <shahab.vahedi@amd.com>
Co-Authored-By: Anurag Kumar <AnuragKumar.Vulisha@amd.com>
Change-Id: I80e76c8ec98b725937fe445883fae707097ec2b7
After commit 5c3261b0e8 there was no need for this flag. Remove it
and tidy places that used it.
include/
* bfdlink.h (struct bfd_link_info): Delete
check_relocs_after_open_input.
ld/
* emultempl/aarch64elf.em (before_parse): Don't set
link_info.check_relocs_after_open_input.
* emultempl/armelf.em (before_parse): Likewise.
* emultempl/elf.em (before_parse): Likewise.
* emultempl/scoreelf.em (before_parse): Likewise.
* emultempl/mmix-elfnmmo.em (mmix_before_parse): Delete.
(LDEMUL_BEFORE_PARSE): Don't define.
* emultempl/mmixelf.em (elfmmix_before_parse): Call elf.em
before_parse.
* ldlang.c (lang_check_relocs): Don't test
link_info.check_relocs_after_open_input.
The CRn and CRm operands of sysp were unnecessarily constrained to the
ranges C8-C9 and C0-C7. This constraint has been removed from the
architecture spec, and was never implemented in LLVM, so remove it here
as well.
Additionally, add some more tests to cover the full range of valid sysp
operands, including omitting the pair of optional operands.
These accept either r or w prefix registers during assembly
(pseudoc dialect), while disassembling canonically as r registers.
This eliminates the need for duplicate opcode table entries for
instructions that accept both w and r register forms.
Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>
This patch removes the constraint that a CTF_F_ARRNELEMS flag has to be
present in order to reverse the elements of an array when dumping. The
flag was never added to GCC, and having this requirement causes more
problems than it solves. A quick recap of the issue:
Given an array int foo[1][2][3], the expected graph is:
int foo[1][2][3] -> int foo[2][3] -> int foo[3] -> int foo
Prior to GCC PR114186, the emitted graph would be:
int foo[1][2][3] -> int foo[1][2] -> int foo[1] -> int foo
Following GCC PR114186, before the libctf fix, the output was:
int foo[3][2][1] -> int foo[3][2] -> int foo[3] -> int foo
So the underlying type graph was correct, but the ordering of elements
was incorrect.
With this fix, we emit correct ordering of the type graph, with no
requirements for the compiler to signal that it has GCC PR114186.
include/
* ctf.h (CTF_F_ARRNELEMS): Delete.
(CTF_F_MAX): Adjust.
libctf/
* ctf-decl.c (ctf_decl_push): Act as if CTF_F_ARRNELEMS is
always set.
* ctf-dump.c (ctf_dump_header): No longer dump its value.
* testsuite/libctf-lookup/multidim-array.c: No longer detect
compilers not emitting this flag (none do).
It looks like assuming _GL_WINDOWS_STAT_INODES is 1 is likely our best
option. See gnulib/m4/windows-stat-inodes.m4. Note that this doesn't
really make SAME_INODE usable on windows hosts as a number of the
likely filesystems (FAT, HPFS, or NTFS) don't support st_ino.
* same-inode.h (SAME_INODE <_WIN32>): Remove _GL_WINDOWS_STAT_INODES
test. Assume it is true.
With commit:
commit f829773772
Date: Tue Mar 25 13:30:32 2025 +0000
Delete the ARM sub-directory of the SIM directory.
the arm simulator was removed from the sim/ directory. GDB has now
been updated to remove its support for the arm simulator, and as a
result, this header file is no longer used by anyone. Lets delete it.
There should be no user visible changes after this commit.
Approved-By: Tom Tromey <tom@tromey.com>
The BPF "may_goto" instruction is a special sort of conditional jump
where the condition is determined by the BPF runtime. That is, it is
a no-op until the runtime decides otherwise.
For normal asm syntax, the mnemonic "jcond" is chosen in keeping with
the style of following the opcode definitions in the Linux kernel uapi
BPF headers.
This instruction is not currently emitted by GCC, but it can be inserted
into BPF programs via macros defined in the Linux kernel.
PR gas/32176
include/
* opcode/bpf.h (BPF_CODE_JCOND): New.
(bpf_insn_id): Add BPF_INSN_JCOND.
opcodes/
* bpf-opc.c: Add entry for BPF_INSN_JCOND.
gas/testsuite/
* gas/bpf/bpf.exp: Run new dump tests.
* gas/bpf/jcond-be-pseudoc.d: New.
* gas/bpf/jcond-be.d: New.
* gas/bpf/jcond-pseudoc.d: New.
* gas/bpf/jcond-pseudoc.s: New.
* gas/bpf/jcond.d: New.
* gas/bpf/jcond.s: New.
The existing SFrame V3 macros for Flexible FDEs used the term 'OFFSET'
to refer to the data word encoding control/register data word. This can
be confusing, as the control data word (register ID, dereference flags)
is distinct from a stack offset.
This patch renames these macros to use 'CTRLWORD' to better reflect
their purpose. It also updates the assembler and libsframe dumper to
use the new nomenclature.
No functional change.
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
gas/
* gen-sframe.c (sframe_get_fre_dataword_size): Use
SFRAME_V3_FLEX_FDE_CTRLWORD_ENCODE.
(output_sframe_row_entry_datawords): Likewise.
include/
* sframe.h (SFRAME_V3_FLEX_FDE_REG_ENCODE): Rename from ..
(SFRAME_V3_FLEX_FDE_CTRLWORD_ENCODE): .. to.
(SFRAME_V3_FLEX_FDE_CTRLWORD_REGNUM): Rename from
SFRAME_V3_FLEX_FDE_OFFSET_REG_NUM to this.
(SFRAME_V3_FLEX_FDE_CTRLWORD_DEREF_P): Rename from
SFRAME_V3_FLEX_FDE_OFFSET_REG_DEREF_P to this.
(SFRAME_V3_FLEX_FDE_CTRLWORD_REG_P): Rename from
SFRAME_V3_FLEX_FDE_OFFSET_REG_P to this.
(SFRAME_V3_FRE_RA_UNDEFINED_P): Add new V3 macro.
libsframe/
* sframe-dump.c (dump_sframe_func_fres_flex): Update all
callers to use the new CTRLWORD macros.
libsframe/testsuite/
* libsframe.decode/be-flipping-v3.c: Use renamed macros.
TLBI Domains feature changes TLBI and TLBIP system instructions.
For all TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS*
instructions that are currently dependent on FEAT_D128 (+d128),
will also be available with FEAT_TLBID (+tlbid).
TLBI Domains feature changes TLBI and TLBIP system instructions.
For the TLBI instruction with optional register argument
<Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to
have an Rt value which is not 0b11111 and this is allowed for
all the TLBI instructions with a <type> of ALLE1*, ALLE2*,
VMALL*, VMALLS12* or VMALLWS2* and a <shareability> of IS or OS.
This patch add support for FEAT_TLBID feature, which is enabled
by new +tlbid option.
This patch is the first patch to align libsframe with the terminology
change of moving from 'offset' to 'data word'. With the introduction of
flexible FDE type SFRAME_FDE_TYPE_FLEX, the variable-length data
following an SFrame FRE header can now represent signed offsets or
unsigned control data. Consequently, 'data word' is adopted as the more
generic term.
This change updates the names used in the user-facing
sframe_frame_row_entry structure. While some API function names remain
unchanged to preserve existing contracts, the underlying data buffers
and size macros now reflect the data word' terminology.
libsframe is a tricky spot for such a terminology change: some of APIs
are still used to read (may be followed by endian swap) for dumping
SFrame V2 sections in textual format. Some classic examples are
sframe_decode_fre, and flip_fre (both are static functions). But moving
forward, using the term 'data word' for such APIs and their internal too
may be better. Subsequent commits will achieve just that.
include/
* sframe-api.h (MAX_NUM_DATAWORDS): Rename from
MAX_NUM_STACK_OFFSETS.
(MAX_DATAWORD_BYTES): Rename from MAX_OFFSET_BYTES.
(struct sframe_frame_row_entry): Rename fre_offsets to
fre_datawords.
libsframe/
* sframe.c (sframe_fre_sanity_check_p): Use MAX_NUM_DATAWORDS.
(sframe_get_fre_offset): Update internal pointers to use
'offsets' and access fre_datawords.
(sframe_get_fre_udata): Rename local variables to
dataword_cnt/dataword_size and update to use
SFRAME_FRE_DATAWORD_* constants.
(sframe_decode_fre): Use fre_datawords and MAX_DATAWORD_BYTES.
(sframe_encoder_add_fre): Use fre_datawords.
(sframe_encoder_write_fre): Use fre_datawords.
In SFrame V3, with the addition of flexible FDE type, the
variable-length array of bytes trailing the SFrame FRE header are no
longer exclusively interpreted as signed offsets. This data can now
include unsigned control data, unsigned padding word data or signed
offset data. Consequently, using the term "offsets" to describe this
trailing data is inaccurate and can be confusing.
This patch switches the terminology to 'Data Word' across the assembler
and the SFrame header file. Note that, the term 'Word' is used
colloquially here, the actual size (1, 2, or 4 bytes) remains determined
by the applicable bits in the FRE info byte.
gas/
* gen-sframe.c: Rename SFrame FRE 'offset' to 'data word'.
include/
* sframe.h (SFRAME_FRE_DATAWORD_1B, SFRAME_FRE_DATAWORD_2B,
SFRAME_FRE_DATAWORD_4B): New constants.
(struct sframe_fre_info): Update bitfield documentation.
(SFRAME_V3_FRE_DATAWORD_COUNT): New macro.
(SFRAME_V3_FRE_DATAWORD_SIZE): New macro.
